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general description the max3540 complete single-conversion televisiontuner is designed for use in analog/digital terrestrial appli- cations and digital set-top boxes. this television tuner draws only 760mw of power from a +3.3v supply voltage. the max3540 is designed to convert ntsc or atsc sig- nals in the 54mhz to 860mhz band to a 44mhz interme- diate fr equency (if). the max3540 includes a variable-gain low-noise ampli-fier (lna), multiband tracking filters, a harmonic-rejec- tion mixer, a low-noise if amplifier, an if power detector, and a variable-gain if amplifier. the max3540 also includes fully monolithic vcos and tank circuits as well as a complete frequency synthesizer. this highly inte- grated design allows for low-power tuner-on-board applications without the cost and power-dissipation issues of dual-conversion tuner solutions. the max3540 is specified for operation in the 0c to +85c temperature range and is available in a leadless 48-pin flip-chip (fclga) package. applications televisionsanalog/digital terrestrial receivers digital set-top boxes cable modems voip gateways features ? low power consumption: 760mw (typ) from a+3.3v supply voltage ? integrated tracking filters ? atsc a/74 compliant ? 40db adjacent channel protection ratio (acpr) ? 4.4db (typ) low noise figure ? small, 7mm x 7mm, fclga leadless package ? 256-qam-compatible phase-noise performance ? if overload detector controls rf variable-gainamplifier ? 2-wire i 2 c-compatible serial control interface max3540 complete single-conversion television tuner ________________________________________________________________ maxim integrated products 1 gndgnd gnd gndgnd v cc gnd ifout2- gnd gndgnd gnd ifovldv cc gnd ifout1-ifout1+ ifin+ ifin- ifagc ifout2+ v cc gnd lext rfgnd3 rfagc v cc gnd + v cc v ref xtalpv cc cp addr2addr1 mux v cc ldov cc vtunegnd_tune xtaln 35 4 6 gnd 78 10 9 1112 vhf_in rfgnd2 2 v cc uhf_in 1 r 3432 33 3130 + - 2927 28 2625 35 36 17 16 21 20 19 18 22 23 24 15 14 13 44 45 n pd cp 40 41 42 43 39 38 37 46 47 48 scl sda max3540 vco divider ep serial interface pin configuration ordering information 19-0848; rev 2; 4/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free/rohs-compliant package. evaluation kit available part temp range pin-package max3540ulm+ 0c to +85c 48 lga-ep* downloaded from: http:///
max3540 complete single-conversion television tuner 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(max3540 evaluation kit, v cc = +3.1v to +3.5v, no rf signals at rf inputs, default register settings, v rfagc = v ifagc = +3v (minimum attenuation), t a = 0c to +85c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25c, unless otherwise noted.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..............................................................-0.3v, +3.6v rfin, ifin_, ifout1_, ifout2_, ifagc, rfagc, vtune, ldo, mux, cp, xtal to gnd ..-0.3v to (v cc + 0.3v) sda, scl, addr2, addr1 to gnd......................-0.3v to +3.6v ifout__ short-circuit duration .....................................indefinite rf input power ...............................................................+10dbm continuous power dissipation (t a = +70c) 48-pin fclga (derate 25mw/c above +70c) ...............1.4w operating temperature range...............................0c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+240c parameter conditions min typ max units supply voltage and current supply voltage +3.1 +3.5 v receive mode 240 275 supply current shutdown mode 5 ma rf and if ag c inp ut bi as c ur r ent at +0.5v and +3v -50 +50 a minimum attenuation +3 rf and if agc control voltage(note 1) maximum attenuation +0.5 v digital input logic-level low 0.3 x v cc v digital input logic-level high 0.7 x v cc v serial interface input logic-level low 0.3 x v cc v input logic-level high 0.7 x v cc v input hysteresis 0.05 x v cc v sda, scl input current -10 +10 a output logic-level low 3ma sink current 0.4 v output logic-level high v cc - 0.5 v caution! esd sensitive device downloaded from: http:///
max3540 complete single-conversion television tuner _______________________________________________________________________________________ 3 parameter conditions min typ max units rf input to ifout1_ output vhf_in, lpf enabled, inpt = 00 54 100 vhf_in, lpf disabled, inpt = 01 100 300 operating frequency range(see table 7) uhf_in, inpt = 10 300 860 mhz analog channel pix carrier 45.75 output frequency digital channel center frequency 44 mhz maximum gain, v rfagc = 3v, 54mhz to 860mhz 34 maximum gain, v rfagc = 3v, broadcast channels 28.0 34 45.5 voltage gain source impedance =75 , load impedance = 200 m i ni m um g ai n, v r fa gc = 0.5v -11 db vhf_in 54 300 operating frequency range gain specification metacross these frequency bands uhf_in 300 860 mhz input return loss worst case, selected channel 8 db noise figure maximum gain, v rfvgc = 3v (note 1) 4.4 db maximum gain, v rfvgc = 3v 15 input ip2(in-band and out-of-band tones) at 12.5db of gain 29 dbm maximum gain, v rfvgc = 3v -13 input ip3(in-band and out-of-band tones) at 12.5db of gain 5 11 dbm maximum gain, v rfvgc = 3v -24.5 input p 1db at 12.5db of gain, cw tone at f c - 36mhz, tested at ch 69 in uhf band -3 dbm beats within output 0dbmv pix carrier level (note 1) -60 dbc vhf_in from 150mhz to 960mhz -60 vhf_in from 960mhz to 1400mhz -40 beats, converted to output uhf_in from 600mhz to 1400mhz -40 dbc gain flatness 54mhz to 60mhz 1.5 db p-p isolation 5mhz to 50mhz, rf input to if output, relative to desiredchannel 60 dbc port-to-port isolation isolation between rf input ports at 215mhz 30 db 54mhz to 860mhz 70 image rejection measured at 91.5mhzabove desired channels center frequency broadcast channels,t a = +25 c 66 dbc 5mhz to 65mhz -40 spurious leakage at rf input 65mhz to 878mhz -40 dbmv 10khz offset -85 100khz offset, 1.5khz loop bandwidth -105 phase noise (single-sideband) 1mhz offset, 1.5khz loop bandwidth -125 dbc/hz output return loss balanced 50 load 9 db ac electrical characteristics(max3540 evaluation kit, v cc = +3.1v to +3.5v, 75 system impedance, default register settings, v rfagc = v ifagc = +3v (minimum attenuation), t a = 0c to +85c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25c, unless otherwise noted.) downloaded from: http:///
max3540 complete single-conversion television tuner 4 _______________________________________________________________________________________ ac electrical characteristics (continued)(max3540 evaluation kit, v cc = +3.1v to +3.5v, 75 system impedance, default register settings, v rfagc = v ifagc = +3v (minimum attenuation), t a = 0c to +85c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25c, unless otherwise noted.) parameter conditions min typ max units if variable-gain amplifier input impedance balanced 2000 output impedance balanced (note 1) 300 maximum gain setting,v ifagc = 3v 54 56 65 passband voltage gain s our ce l oad = 300 , outp ut l oad = 300 minimum gain setting,v ifagc = 0.5v 21 db passband gain flatness 40mhz to 48mhz (note 1) 1.2 db output voltage v ifagc = 3v (note 1) 2 v p-p agc gain slope v ifagc = 3v to 0.5v (note 1) 30 db/v equivalent input voltagenoise density at 44mhz, maximum gain, v ifagc = 3v (note 1) 7.3 nv/ hz noise figure change vs.attenuation < 0.35 db/db im3 v out = 1.5v p-p , 40db < gain < 60db (note 1) -54 dbc if overload detector (see the if overload detector section) output overload attack point 0.7 v p-p attack-point accuracy 1 db detector output voltage range negative polarity, overload reduces v det (open collector, 0.3ma sink) 0.5 3.0 v detector gain 70 v/v frequency synthesizer reference oscillator frequency 4 mhz dividers rf n-divider ratio 256 32,767 rf r-divider ratio 81 2 7 lo phase detector and charge pump comparison frequency 31.50 250.00 khz cp = 00 0.5 cp = 01 1 cp = 10 1.5 charge-pump current cp = 11 2 ma c har g e- p um p thr ee- s tate c ur r ent 5 na charge-pump current matching 5% local oscillator (oscillator with narrow band loop) vco tuning range tank frequency 2160 4400 mhz vco tuning gain tank oscillator gain 500 mhz/v 2-wire serial interface clock frequency 400 khz note 1: guaranteed by design and characterization. downloaded from: http:///
max3540 complete single-conversion television tuner _______________________________________________________________________________________ 5 typical operating characteristics (max3540 evaluation kit, v cc = +3.3v, f rf = 83mhz (vhf low), 211mhz (vhf high), or 801mhz (uhf), f if = 45.75mhz, t a = +25c, unless otherwise noted.) supply current vs. supply voltage supply voltage supply current (ma) max3540 toc01 3.1 3.2 3.3 3.4 3.5 216 220 224 228 232 236 t a = 0 c t a = +85 c t a = +25 c vhf-l voltage gain vs. rf vga voltage rf vga (v) voltage gain (db) max3540 toc02 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -30 -20 -10 0 10 20 30 40 50 t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-h voltage gain vs. rf vga voltage rf vga (v) voltage gain (db) max3540 toc03 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -30 -20 -10 0 10 20 30 40 50 t a = +85 c t a = +55 c t a = 0 c t a = +25 c uhf voltage gain vs. rf vga voltage rf vga (v) voltage gain (db) max3540 toc04 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -30 -20 -10 0 10 20 30 40 50 t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-l voltage gain vs. frequency frequency (mhz) voltage gain (db) max3540 toc05 50 80 110 140 170 200 10 15 20 25 30 35 40 45 t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-h voltage gain vs. frequency frequency (mhz) voltage gain (db) max3540 toc06 200 250 300 350 400 450 10 15 20 25 30 35 40 45 t a = +85 c t a = +55 c t a = 0 c t a = +25 c uhf voltage gain vs. frequency frequency (mhz) voltage gain (db) max3540 toc07 400 500 600 700 800 900 10 15 20 25 30 35 40 45 t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-l noise figure vs. frequency frequency (mhz) noise figure (db) max3540 toc08 40 60 80 100 120 140 160 180 200 220 1 3 5 7 t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-h noise figure vs. frequency frequency (mhz) noise figure (db) max3540 toc09 180 230 280 330 380 430 480 2 4 6 8 t a = +85 c t a = +55 c t a = 0 c t a = +25 c downloaded from: http:///
max3540 complete single-conversion television tuner 6 _______________________________________________________________________________________ uhf noise figure vs. frequency frequency (mhz) noise figure (db) max3540 toc10 400 450 500 550 600 650 700 750 800 850 900 2 4 6 8 10 t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-l noise figure vs. rfagc voltage rfagc voltage (v) noise figure (db) max3540 toc11 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 30 35 f rf = 181.25mhz t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-h noise figure vs. rfagc voltage rfagc voltage (v) noise figure (db) max3540 toc12 0 5 10 15 20 25 30 35 1.5 2.0 2.5 3.0 3.5 f rf = 331.25mhz t a = +85 c t a = +25 c t a = 0 c t a = +55 c uhf noise figure vs. rf agc voltage rf agc voltage (v) noise figure (db) max3540 toc13 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 f rf = 657.25mhz t a = +85 c t a = +55 c t a = 0 c t a = +25 c vhf-l image rejection vs. frequency frequency (mhz) vhf-l image rejection (db) max3540 toc14 40 60 80 100 120 140 160 180 200 220 60 65 70 75 80 85 90 t a = +85 c t a = 0 c t a = +25 c vhf-h image rejection vs. frequency frequency (mhz) vhf-h image rejection (db) max3540 toc15 150 200 250 300 350 400 450 500 60 65 70 75 80 85 90 t a = +85 c t a = 0 c t a = +25 c uhf image rejection vs. frequency frequency (mhz) uhf image rejection (db) max3540 toc16 400 500 600 700 800 900 60 65 70 75 80 85 90 t a = +85 c t a = 0 c t a = +25 c vhf-l phase noise at 10khz offset vs. channel frequency frequency (mhz) phase noise (dbc/hz) max3540 toc17 0 50 100 150 200 250 -101 -100 -99 -98 -97 -96 -95 -94 vhf-h phase noise at 10khz offset vs. channel frequency frequency (mhz) phase noise (dbc/hz) max3540 toc18 190 210 230 250 270 290 310 -96.5 -96.0 -95.5 -95.0 -94.5 -94.0 -93.5 -93.0 -92.5 -92.0 typical operating characteristics (continued) (max3540 evaluation kit, v cc = +3.3v, f rf = 83mhz (vhf low), 211mhz (vhf high), or 801mhz (uhf), f if = 45.75mhz, t a = +25c, unless otherwise noted.) downloaded from: http:///
max3540 complete single-conversion television tuner _______________________________________________________________________________________ 7 typical operating characteristics (continued) (max3540 evaluation kit, v cc = +3.3v, f rf = 83mhz (vhf low), 211mhz (vhf high), or 801mhz (uhf), f if = 45.75mhz, t a = +25c, unless otherwise noted.) uhf phase noise at 10khz offset vs. channel frequency frequency (mhz) phase noise (dbc/hz) max3540 toc19 200 300 400 500 600 700 800 900 1000 -96 -94 -92 -90 -88 -86 -84 -82 vhf-l phase noise vs. offset frequency offset frequency (khz) phase noise (dbc/hz) max3540 toc20 -130 -120 -110 -100 -90 -80 -70 -60 0.1 1 10 100 1000 vhf-h phase noise vs. offset frequency offset frequency (khz) phase noise (dbc/hz) max3540 toc21 -130 -120 -110 -100 -90 -80 -70 -60 0.1 1 10 100 1000 uhf phase noise vs. offset frequency offset frequency (khz) phase noise (dbc/hz) max3540 toc22 -130 -120 -110 -100 -90 -80 -70 -60 0.1 1 10 100 1000 ifout1 frequency response frequency (mhz) output (dbm) max3540 toc23 -30 -25 -20 -15 -10 -5 0 0.01 0.1 1 10 100 1000 if vga voltage gain vs. if vga if vga (v) voltage gain (db) max3540 toc24 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 50 60 t a = +55 c t a = +85 c t a = 0 c t a = +25 c if vga im3 vs. if agc voltage if agc (v) if vga im3 (dbc) max3540 toc25 input power (dbm) -80 -60 -40 -20 0.5 1.0 1.5 2.0 2.5 3.0 -60 -50 -40 -30 -20 p in im3 v out = 1.5v pp downloaded from: http:///
max3540 complete single-conversion television tuner 8 _______________________________________________________________________________________ pin description pin name function 1 scl 2-wire serial-clock interface. requires a pullup resistor to v cc . 2 sda 2-wire serial-data interface. requires a pullup resistor to v cc . 3, 10, 23, 28, 32, 33, 37, 41, 44 v cc power-supply connections. bypass each supply pin to ground with a 1000pf capacitor. 4 uhf_in uhf rf input. matched to 75 over the operating band. requires a dc-blocking capacitor. 5 vhf_in vhf rf input. matched to 75 over the operating band. requires a dc-blocking capacitor. 6 rfgnd2 rf ground. bypass to the pcbs ground plane with a 1000pf capacitor. do not connect rfgnd2 and rfgnd3 together. 7 lext rf vga supply voltage. connect through a 270nh pullup inductor to v cc . 8 rfgnd3 rf ground. bypass to the pcbs ground plane with a 1000pf capacitor. do not connect rfgnd2 and rfgnd3 together. 9 rfagc rf ag c g ai n- c ontr ol v ol tag e. accep ts a d c vol tag e fr om 0.5v ( m i ni m um g ai n) to 3v ( m axi m um g ai n) . 11C22, 27, 31 gnd ground. connect to the pcbs ground plane. 24 ifout2- inver ti ng if- v g a outp ut. c onnect to the i np ut of an anti - al i asi ng fi l ter . req ui r es a d c - b l ocki ng cap aci tor . 25 ifout2+ noninverting if-vga output. connect to the input of an anti-aliasing filter. requires a dc-blockingcapacitor. 26 ifagc if agc gain-control voltage. accepts a dc voltage from 0.5v (minimum gain) to 3v (maximum gain). 29 ifin- inverting if-vga input. connect to the output of an if-saw filter. 30 ifin+ noninverting if-vga input. connect to the output of an if-saw filter. 34 ifovld if power detector open-collector output. requires a 10k pullup resistor to v cc . 35 ifout1+ n oni nver ti ng if- ln a outp ut. req ui r es a d c - b l ocki ng cap aci tor . 36 ifout1- inverting if-lna output. requires a dc-blocking capacitor. 38 ldo vco ldo bypass. bypass to ground with a 0.47f capacitor. 39 gnd_tune vtune ground connection. connect to the pcb ground plane. all loop filter component gnd mustbe connected to this pin (see the typical application circuit ). 40 vtune vco tuning input. connect to the pll loop filter output. 42 mux test output. leave this pin unconnected during normal operation. 43 cp charge-pump output. connect to the pll loop filter input. 45 xtaln crystal oscillator feedback. see the typical application circuit . 46 xtalp crystal input. requires a dc-blocking capacitor. 47 addr1 2-wire serial-interface address line 1. this pin along with addr2 sets the device address for thei 2 c-compatible serial interface. 48 addr2 2-wire serial-interface address line 2. this pin along with addr1 sets the device address for thei 2 c-compatible serial interface. ep ep exposed paddle. solder evenly to the pcb ground plane for proper operation. downloaded from: http:///
max3540 complete single-conversion television tuner _______________________________________________________________________________________ 9 detailed description register descriptions the max3540 includes 11 programmable registers andtwo read-only registers. the 11 programmable registers include two n-divider registers, an r-divider register, a vco register, an rssi/charge-pump/filter-select regis- ter, a control register, a shutdown register, and tracking- filter control registers. these 11 programmable regis-ters are also readable. the read-only registers include a status register and a rom table data register. recommended default bit settings are provided for user convenience only and are not guaranteed. the user must write all registers after power-up and no ear- lier than 100s after power-up. msb lsb data byte register name r ea d / w r i t e register address d7 d6 d5 d4 d3 d2 d1 d0 n-div high both 0x00 0 n14 n13 n12 n11 n10 n9 n8 n-div low both 0x01 n7 n6 n5 n4 n3 n2 n1 n0 r-div both 0x02 0 r6 r5 r4 r3 r2 r1 r0 vco both 0x03 vco4 vco3 vco2 vco1 vco0 ld vdiv1 v d iv 0 ifovld, charge pump, and filter select both 0x04 0 ifovld2 ifovld1 ifovld0 cp1 cp0 tf1 tf0 control both 0x05 0 0 0 0 shdn_rf shdn_ifagc inpt1 in p t0 shutdown both 0x06 s h d n _m ix 1 s h d n _m ix 0 s h d n _i f s h d n _p d s h d n _s y n 0 0 0 tracking filter series cap both 0x07 tfs7 tfs6 tfs5 tfs4 tfs3 tfs2 tfs1 tfs0 tracking filter parallel cap both 0x08 fld 0 tfp5 tfp4 tfp3 tfp2 tfp1 tfp0 tracking filter rom address both 0x09 0 0 0 0 tfa3 tfa2 tfa1 tfa0 reserved both 0x0a x x x x x x x x rom table data readback read 0x0b tfr7 tfr6 tfr5 tfr4 tfr3 tfr2 tfr1 tfr0 status read 0x0c por ld2 ld1 ld0 x x x x table 1. register configuration bit name bit location (0 = lsb) recommended default function reserved 7 0 must be set to 0. n[14:8] 6C0 001 0010 sets the most significant bits of the pll integer divider (n). d efault integer divider value is n = 4688. n can range from 256 to 32,767. table 2. n-div high register (address: 0000 b ) downloaded from: http:///
max3540 complete single-conversion television tuner 10 ______________________________________________________________________________________ bit name bit location (0 = lsb) recommended default function reserved 7 0 must be set to 0. r[6:0] 6C0 100 0000 sets the pll reference divider (r). default reference divider value is r = 64. r can range from 16 to 127. table 4. r-div register (address: 0010 b ) bit name bit location (0 = lsb) recommended default function vco[4:3] 7, 6 01 vco select. selects one of three possible vcos. 00 = vcos shut down 01 = selects vco1 10 = selects vco2 11 = selects vco3 vco[2:0] 5, 4, 3 101 vco sub-band select. selects one of eight possible vco sub-bands. 000 = selects sb0 001 = selects sb1 010 = selects sb2 011 = selects sb3 100 = selects sb4 101 = selects sb5 110 = selects sb6 111 = selects sb7 ld 2 1 lock-detect enable.0 = disabled 1 = enabled vdiv[1:0] 1, 0 01 vco divider ratio select. 00 = sets v c o d i vi d er to 4 01 = sets v c o d i vi d er to 8 10 = sets vco divider to 1611 = sets vco divider to 32 table 5. vco register (address: 0011 b ) bit name bit location (0 = lsb) recommended default function n[7:0] 7C0 0101 0000 sets the least significant bits of the pll integer divider (n). defaultinteger divider value is n = 4688. n can range from 256 to 32,767. table 3. n-div low register (address: 0001 b ) downloaded from: http:///
max3540 complete single-conversion television tuner ______________________________________________________________________________________ 11 bit name bit location (0 = lsb) recommended default function reserved 7 0 must be set to 0. ifo v ld [ 2:0] 6, 5, 4 000 write content of rom register od[2:0] to this location. cp[1:0] 3, 2 00 selects the typical charge-pump current.00 = 0.5ma 01 = 1ma 10 = 1.5ma 11 = 2ma tf[1:0] 1, 0 00 selects the tracking filter band of operation.00 = vhf low 01 = vhf high 10 = uhf 11 = factory use only table 6. rssi, charge pump, and filter select register (address: 0100 b ) bit name bit location (0 = lsb) recommended default function reserved 7C4 0000 must be set to 0000. shdn_rf 3 0 rf shutdown. 0 = rf circuitry enabled 1 = rf circuitry disabled shdn_ifv ga 2 1 if vga shutdown. 0 = if vga enabled 1 = if vga disabled inpt[1:0] 1, 0 00 selects the rf input. 00 = selects vhf_in with lpf 01 = selects vhf_in, no lpf 10 = selects uhf_in 11 = factory use only table 7. control register (address: 0101 b ) downloaded from: http:///
max3540 complete single-conversion television tuner 12 ______________________________________________________________________________________ bit name bit location (0 = lsb) recommended default function shdn_mix 7, 6 0 mixer shutdown.00 = mixer enabled 01, 10 = factory use only 11 = mixer disabled shdn_if 5 0 if shutdown.0 = if section enabled 1 = if section disabled shdn_pd 4 0 if ovld shutdown.0 = power detector enabled 1 = power detector disabled shdn_syn 3 0 frequency synthesizer shutdown.0 = synthesizer enabled 1 = synthesizer disabled reserved 2, 1, 0 000 must be set to 000. table 8. shutdown register (address: 0110 b ) bit name bit location (0 = lsb) recommended default function tfs[7:0] 7C0 00000000* programs series capacitor values in the tracking filter. table 9. tracking-filter series cap register (address: 0111 b ) bit name bit location (0 = lsb) recommended default function fld 7 0 filter load bit. a 0 to 1 transition of this bit forces the loading of therom table data readback register. reserved 6 0 must be set to 0. tfp[5:0] 5C0 000000* programs parallel capacitor values in the tracking filter. table 10. tracking-filter parallel cap register (address: 1000 b ) bit name bit location (0 = lsb) recommended default function reserved 7C4 0000 must be set to 0000. tfa[3:0] 3C0 0000* address bits of the rom register to be read. table 11. tracking-filter rom address register (address: 1001 b ) bit name bit location (0 = lsb) recommended default function reserved 7C0 n/a reserved. do not program these bits during normal operation. table 12. reserved register (address: 1010 b ) * see the rf tracking filter section. downloaded from: http:///
max3540 complete single-conversion television tuner ______________________________________________________________________________________ 13 2-wire serial interface the max3540 uses a 2-wire i 2 c-compatible serial inter- face consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facilitate bidirectional communication between the max3540 and the master at clock frequencies up to 400khz. the master initiates a data transfer on the bus and generates the scl signal to permit data transfer. the max3540 behaves as a slave device that transfers and receives data to and from the master. pull sda and scl high with external pullup resistors (1k or greater) for proper bus operation. one bit is transferred during each scl clock cycle. aminimum of nine clock cycles is required to transfer a byte in or out of the max3540 (8 data bits and an ack/nack). the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control sig- nals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi-tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high. acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit(ack) or a not-acknowledge bit (nack). both the mas- ter and the max3540 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of theacknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. slave address the max3540 has a 7-bit slave address that must besent to the device following a start condition to initi- ate communication. the slave address is determined by the state of the addr2 and addr1 pins and is equal to 11000[addr2][addr1]. the 8th bit (r/ w ) fol- lowing the 7-bit address determines whether a read or write operation will occur. table 15 shows the possible address configurations. bit name bit location (0 = lsb) recommended default function tfr[7:0] 7C0 00000000* tracking-filter data bits read from the devices rom table. table 13. rom table data readback register (address: 1011 b ) bit name bit location (0 = lsb) recommended default function por 7 0 power-on reset.0 = status register has been read 1 = power reset since last status register read ld[2:0] 6, 5, 4 000 vco tuning voltage indicators.000 = pll not in lock, tune to the next lowest sub-band 001C110 = pll in lock 111 = pll not in lock, tune to the next higher sub-band reserved 3C0 0000 reserved. table 14. status register (address: 1100 b ) addr2 addr1 write address read address 0 0 0xc0 0xc1 0 1 0xc2 0xc3 1 0 0xc4 0xc5 1 1 0xc6 0xc7 table 15. max3540 address configurations * see the rf tracking filter section. downloaded from: http:///
max3540 complete single-conversion television tuner 14 ______________________________________________________________________________________ the max3540 continuously awaits a start conditionfollowed by its slave address. when the device recog- nizes its slave address, it acknowledges by pulling the sda line low for one clock period. it is ready to accept or send data depending on the r/ w bit (figure 1). write cycle when addressed with a write command, the max3540allows the master to write to a single register or to multi- ple successive registers. a write cycle begins with the bus master issuing a start condition followed by the 7 slave address bits and a write bit (r/ w = 0). the max3540 issues an ack if the slave address byte is successfully received. thebus master must then send to the slave the address of the first register it wishes to write to. if the slave acknowledges the address, the master can then write one byte to the register at the specified address. data is written beginning with the most significant bit. the max3540 again issues an ack if the data is success- fully written to the register. the master can continue to write data to the successive internal registers with the max3540 acknowledging each successful transfer, or it can terminate transmission by issuing a stop condi- tion. the write cycle does not terminate until the master issues a stop condition. figure 2 illustrates an example in which registers 0 through 2 are written with 0x0e, 0xd8, and 0xe1, respectively. read cycle a read cycle begins with the bus master issuing astart condition followed by the seven slave address bits and a write bit (r/ w = 0). the max3540 issues an ack if the slave address byte is successfully received.the master then sends the 8-bit address of the first reg- ister that it wishes to read. the max3540 then issues another ack. next, the master must issue a start con- dition followed by the 7 slave address bits and a read bit (r/ w = 1). the max3540 issues an ack if it success- fully recognizes its address and begins sending datafrom the specified register address starting with the most significant bit (msb). data is clocked out of the max3540 on the rising edge of scl. on the 9th rising edge of scl, the master can issue an ack and contin- ue reading successive registers or it can issue a nack followed by a stop condition to terminate transmission. the read cycle does not terminate until the master issues a stop condition. figure 3 illustrates an example in which registers 0 and 1 are read back. scl sda 123456789 s 11000 addr2 addr1 r/w ack slave address p note: timing parameters conform with i 2 c bus specifications. figure 1. max3540 slave address byte write device address r/ w ack write register address ack write data to register 0x00 ack write data to register 0x01 ack write data to register 0x02 ack start 11000[addr2][addr1] 0 0x00 0x0e 0xd8 0xe1 stop figure 2. example: write registers 0 through 2 with 0x0e, 0xd8, and 0xe1, respectively. write device address r/ w ack write 1st register address ack write device address r/ w ack read data reg 0 ack read data reg 1 nack start 110000[addr2][addr1] 0 0x00 start 110000[addr2][addr1] 1 d7?0 d7?0 stop figure 3. example: read data from registers 0 through 1. downloaded from: http:///
max3540 complete single-conversion television tuner ______________________________________________________________________________________ 15 applications information rf inputs the max3540 features separate uhf and vhf inputsthat are matched to 75 . both inputs require a dc-block- ing capacitor. the input registers select the active inputs.in addition, the input registers enable or disable the low- pass filter, which can be used when the vhf input is selected. for 54mhz to 100mhz, select the vhf_in with the lpf filter enabled (inpt = 00). for 100mhz to 300mhz, select vhf_in with lpf disabled (inpt = 01). for 300mhz to 860mhz, select uhf_in (inpt = 10). rf gain control the gain of the rf low-noise amplifier can be adjustedover a typical 45db range by the rfagc pin. the rfagc input accepts a dc voltage from 0.5v to 3v, with 3v providing maximum gain. this pin can be con- trolled with the if power-detector output to form a closed rf gain-control loop. see the closed-loop rf gain control section for more information. rf tracking filter the max3540 includes a programmable tracking filter foreach band of operation to optimize rejection of out-of- band interference while minimizing insertion loss for the desired received signal. vhf low, vhf high, or uhf track- ing filter is selected by the tf register. the center fre- quency of each tracking filter is selected by a switched-capacitor array, which is programmed by the tfs[7:0] bits in the tracking-filter series cap register and the tfp[5:0] bits in the tracking-filter parallel cap register. to accommodate part-to-part variations each part is fac- tory-calibrated by maxim. during calibration the y-inter- cept and slope for the series and parallel tracking capacitor arrays is calculated and written into an internal rom table. the user must read the rom table upon power-up and store the data in local memory (8 bytes total) to calculate the optimal tfs[7:0] and tfp[5:0] set- tings for each channel. table 16 shows the address and bits for each rom table entry. see the interpolating tracking filter coefficients section for more information on how to calculate the required values. reading the rom table each rom table entry must be read using a two-step process. first, the address of the rom bits to be read must be programmed into the tfa[3:0] bits in the tracking filter rom address register (table 11). once the address has been programmed, the data stored in that address is transferred to the tfr[7:0] bits in the rom table data readback register (table 13). the rom data at the specified address can then be read from the tfr[7:0] bits and stored in the micro- processors local memory. msb l sb data byte description address d7 d6 d5 d4 d3 d2 d1 d0 ifovld 0x0 od2 od1 od0 x x x x x vhf low series/ parallel y-intercept 0x1 ls0[5] ls0[4] ls0[3] ls0[2] ls0[1] ls0[0] ls1[3] ls1[2] vhf high series/ parallel y-intercept 0x2 ls1[1] ls1[0] lp0[5] lp0[4] lp0[3] lp0[2] lp0[1] lp0[0] uhf series/ parallel y-intercept 0x3 lp1[3] lp1[2] lp1[1] lp1[0] hs0[3] hs0[2] hs0[1] hs0[0] vhf low series slope 0x4 hs1[3] hs1[2] hs1[1] hs1[0] hp0[3] hp0[2] hp0[1] hp0[0] vhf high parallel slope 0x5 hp1[3] hp1[2] hp1[1] hp1[0] us0[7] us0[6] us0[5] us0[4] vhf low parallel slope 0x6 us0[3] us0[2] us0[1] us0[0] us1[5] us1[4] us1[3] us1[2] vhf high parallel slope 0x7 us1[1] us1[0] up0[7] up0[6] up0[5] up0[4] up0[3] up0[2] uhf parallel slope 0x8 up0[1] up0[0] up1[5] up1[4] up1[3] up1[2] up1[1] up1[0] table 16. rom table downloaded from: http:///
max3540 complete single-conversion television tuner 16 ______________________________________________________________________________________ interpolating tracking filter coefficients the tfs[7:0] and tfp[5:0] bits must be reprogrammedfor each channel frequency to optimize performance. the optimal settings for each channel can be calculated from the rom table data using the equations below. vhf lo filter: vhf high filter: uhf filter: where: f rf = operating frequency in mhz tfs = decimal value of the optimal tfs[7:0] setting (table 9) for the given operating frequency tfp = decimal value of the optimal tfp[5:0] setting (table 10) for the given operating frequency ls0, ls1, lp0, lp1, hs0, hs1, hp0, hp1, us0, us1, up0, and up1 = the decimal values of the rom table coefficients (table 16). if overload detector the max3541 includes a broadband if overload detec-tor, which provides an indication of the total power pre- sent at the rf input. the overload-detector output voltage is compared to a reference voltage and the dif- ference is amplified. this error signal drives an open- collector transistor whose collector is connected to the ifovld pin, causing the ifovld pin to sink current. the nominal full-scale current sunk by the ifovld pinis 300a. the ifovld pin requires a 10k pullup resis- tor to v cc . the if overload detector is calibrated at the factory toattack at 0.6v p-p at ifout1. upon power-up, the base- band processor must read od[2:0] from the rom tableand store it in the ifvold register. closed-loop rf gain control closed-loop rf gain control can be implemented byconnecting the ifovld output to the rfagc input. using a 10k pullup resistor on the ifovld pin, as shown in the typical application circuit , results in a nominal 0.5v to 3v control voltage range. vco and vco divider selection the max3540 frequency synthesizer includes three vcosand eight vco sub-bands to guarantee a 2160mhz to 4400mhz vco frequency range. the frequency synthesiz- er also features an additional vco frequency divider, which must be programmed to either 4, 8, 16, or 32 through the vdiv[1:0] bits in the vco register based on the channel being received. table 5 describes how the vdiv[1:0] bits should be programmed for each band of operation. to ensure pll, lock the proper vco and vco sub-band for the channel being received, which must be chosen byiteratively selecting a vco and vco sub-band then read- ing the ld[2:0] bits to determine if the pll is locked. anyreading from 001 to 110 indicates the pll is locked. if ld[2:0] reads 000, the pll is unlocked and the selected vco is at the bottom of its tuning range; a lower vco sub- band must be selected. if ld[2:0] reads 111, the pll is unlocked and the selected vco is at the top of its tuning range; a higher vco sub-band must be selected. the vco and vco sub-band settings should be progressively increased or decreased until the ld[2:0] reading falls inthe 001 to 110 range. due to overlap between vco sub-band frequencies, it is possible that multiple vco settings can be used to tune to the same channel frequency. system performance at a given channel should be similar between the various pos- sible vco settings, so it is sufficient to select the first vco and vco sub-band that provides lock. layout considerations the max3540 ev kit can serve as a guide for pcb layout.keep rf signal lines as short as possible to minimize losses and radiation. use controlled impedance on all high-frequency traces. the exposed paddle must be sol- dered evenly to the boards ground plane for proper operation. use abundant vias beneath the exposed pad- dle for maximum heat dissipation. use abundant ground vias between rf traces to minimize undesired coupling. tfp int 10 [(1.6 up0 256 0.8) up1 6 = +++ (. 14 44 0.8 ) f 10 ] rf -3 10 ? ? ? ? ? ? ? ? ? ? tfs int 10 [(3 us0 256 ) us1 64 0.8 ) = +++ (. 26 f 10 ] rf -3 20 ? ? ? ? ? ? ? ? ? ? tfp int 10 [(1.6 hp0 16 0.8) hp1 16 = +++ (. 15 0 0.6 ) f 10 ] rf -3 10 ? ? ? ? ? ? ? ? ? ? tfs int 10 [(2.8 hs0 16 0.8) hs1 16 0.8 ) = +++ (. 42 ? ? ? ? ? ? ? ? ? ? f10] rf -3 20 tfp int 10 [(1.6 lp0 64 0.4) lp1 16 2 = +++ (6 ) )f 10 ] rf -3 ? ? ? ? ? ? ? ? ? ? tfs = int 10 [(2.4 ls0 64 0.6) ls1 16 2) +++ (. 85 f 10 ] rf -3 ? ? ? ? ? ? ? ? ? ? downloaded from: http:///
max3540 complete single-conversion television tuner ______________________________________________________________________________________ 17 gndgnd gnd gndgnd v cc gnd ifout2- gnd gndgnd gnd ifovldv cc gnd ifout1- *connect to common ground point at pin 39. ifout1+ifin+ ifin- ifagc ifout2+ v cc gnd lext rfgnd3 rfagc v cc gnd v cc v ref xtalpv cc cp addr2addr1 mux v cc ldov cc vtunegnd_tune xtaln 35 4 6 gnd 78 10 9 1112 vhf_in rfgnd2 2 v cc uhf_in 1 r 3432 33 3130 + - 2927 28 2625 35 36 17 16 21 20 19 18 22 23 24 15 14 13 44 45 n pd cp 40 41 42 43 39 38 37 46 47 48 scl sda max3540 vco divider ep serial interface 100pf 22pf 1000pf 1000pf 470nf 2.7k v ifagc ifout+ ifovld ifout- 270 2.7 100 ifovld sdata sclk address2 address1 1.3k ** * * 2.7k 2.7k 10k 0.033 f 2.2pf 470pf 100pf 1000pf v cc 1000pf v cc v cc 0.1 f 1000pf v cc v cc v cc 1000pf v cc 1000pf 1000pf 47 f 4700pf v cc v cc 1000pf 0.1 f 1000pf 0.1 f v cc 1000pf v cc v cc 1000pf anti-aliasing filter 680nh 1000pf 1000pf if-sawfilter saw driver amplifier typical application circuit to minimize coupling between different sections of theic, the ideal power-supply layout is a star configura- tion, which has a large decoupling capacitor at the central v cc node. the v cc traces branch out from this node, with each trace going to separate v cc pins of the max3540. each v cc pin must have a bypass capacitor with a low impedance to ground at the fre-quency of interest. do not share ground vias among multiple connections to the pcb ground plane. downloaded from: http:///
18 ______________________________________________________________________________________ complete single-conversion television tuner max3540 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 48 lga-ep l4877a-e 21-0152 downloaded from: http:///
max3540 complete single-conversion television tuner maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/07 initial release 1 12/07 added tpical operating characteristics section, updated package outline 5, 6, 7, 18, 19 2 4/08 converted part number in ordering information to lead-free 1 downloaded from: http:///

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